Generally, an integrated circuit (IC) includes a combination of NMOS (n type Metal-Oxide-Semiconductor) transistors and PMOS (p type Metal-Oxide-Semiconductor) transistors formed on a substrate. In order to increase the efficiency of the very large scale integrated circuits and to reduce the manufacturing costs, a continuous trend is to reduce the feature size of the device, especially the length of the gate. However, the reduction in the length of the gate will result in short-channel effects, thus degrading the performances of the semiconductor device and the whole integrated circuit.
The SOI (Silicon-On-Insulator) technique is to introduce a buried oxide layer (BOX) between the top layer silicon and the substrate. The existence of the buried oxide layer enables a complete dielectric isolation between elements in the integrated circuit, so the SOI-CMOS integrated circuit substantially avoids the parasitic latch-up effect in the bulk silicon CMOS circuit. Meanwhile, in the complete depletion type SOI device, short-channel effects are small, a shallow junction can be naturally formed, and the leakage is small. Therefore, the complete depletion SOI-MOSFET having an ultrathin SOI and dual gates have attracted wide attention. In order to adjust the threshold voltage and to suppress the short-channel effects, a ground plane, which is sometimes used for connecting to the semiconductor layer, is formed under the ultrathin oxide buried layer in the SOI-MOSFET device, and the ground plane is made to have a low resistance so as to form a back-gate structure of the transistor. However, according to conventional methods, in order to connect the ground planes of the NMOSFET and PMOSFET to the respective voltage sources, extra contacts and interconnections are needed, resulting in an increase in the area occupied by the device.
Hence, there is a need for an improved method to connect the ground planes of the NMOSFET and PMOSFET to the respective voltage sources to reduce the area occupied by the device.